#ifndef _SSI_H_
#define _SSI_H_

/* privilege */
typedef volatile        _rw;
typedef volatile        _wo;
typedef volatile const  _ro;
typedef const           _rsvd;  // reserved

// #define SSI_ADDR_BASE
// #define SSI_BRIDGE_BASE


typedef struct {
    /* block 1 */
    _rw   uint32_t CTRLR0;
    _rw   uint32_t CTRLR1;
    _rw   uint32_t SSIENR; // enable.  enable=1, disable
    _rw   uint32_t MWCR;
    _rw   uint32_t SER;
    _rw   uint32_t BAUDR;
    _rw   uint32_t TXFTLR;
    _rw   uint32_t RXFTLR;
    _rw   uint32_t TXFLR;
    _rw   uint32_t RXFLR;
    _rw   uint32_t SR;
    _rw   uint32_t IMR;
    _rw   uint32_t ISR;
    _rw   uint32_t RISR;
    _rw   uint32_t TXEICR;
    _rw   uint32_t RXOICR;
    _rw   uint32_t RXUICR;
    _rw   uint32_t MSTICR;
    _rw   uint32_t ICR;
    _rw   uint32_t DMACR;
    _rw   uint32_t DMATDLR;
    _rw   uint32_t AXIAWLEN;
    _rw   uint32_t DMARDLR;
    _rw   uint32_t AXIARLEN;
    _rw   uint32_t IDR;
    _rw   uint32_t SSIC_VERSION_ID;
    _rw   uint32_t DR[36];
    _rw   uint32_t RX_SAMPLE_DELAY;
    _rw   uint32_t SPI_CTRLR0;
    _rw   uint32_t DDR_DRIVE_EDGE;
    _rw   uint32_t XIP_MODE_BITS;

    /* block 2 */
    _rw   uint32_t XIP_INCR_INST;
    _rw   uint32_t XIP_WRAP_INST;
    _rw   uint32_t XIP_CTRL;
    _rw   uint32_t XIP_SER;
    _rw   uint32_t XRXOICR;
    _rw   uint32_t XIP_CNT_TIME_OUT;
    _rw   uint32_t SPI_CTRLR1;
    _rw   uint32_t SPITECR;
    _rw   uint32_t SPIDR;
    _rw   uint32_t SPIAR;
    _rw   uint32_t AXIAR0;
    _rw   uint32_t AXIAR1;
    _rw   uint32_t AXIECR;
    _rw   uint32_t DONECR;
    _rsvd uint32_t _RESERVED_138;
    _rsvd uint32_t _RESERVED_13C;
    _rw   uint32_t XIP_WRITE_INCR_INST;
    _rw   uint32_t XIP_WRITE_WRAP_INST;
    _rw   uint32_t XIP_WRITE_CTRL;
} ssi_addr_t;


typedef struct {
    _rw   uint32_t CTRLR0;
    _rsvd uint32_t _RESERVED_04;
    _rw   uint32_t SSIENR;
    _rsvd uint32_t _RESERVED_0C;
    _rsvd uint32_t _RESERVED_10;
    _rw   uint32_t RXFBTR;
    _rw   uint32_t TXFTLR;
    _rw   uint32_t RXFTLR;
    _rsvd uint32_t _RESERVED_20;
    _rsvd uint32_t _RESERVED_24;
    _ro   uint32_t SR;
    _rw   uint32_t IMR;
    _ro   uint32_t ISR;
    _ro   uint32_t RISR;
    _ro   uint32_t TXUICR;
    _ro   uint32_t RXOICR;
    _ro   uint32_t SPIMECR;
    _ro   uint32_t AHBECR;
    _ro   uint32_t ICR;
    _rsvd uint32_t _RESERVED_4C;
    _rsvd uint32_t _RESERVED_50;
    _rsvd uint32_t _RESERVED_54;
    _ro   uint32_t IDR;
    _ro   uint32_t SSIC_VERSION_ID;
} ssi_bridge_t;


#define SSI_IS_MST  

#endif


